A Clock Data Recovery (CDR) circuit needs to track data rate variations. A conventional Phase Locked Loop (PLL)-based CDR circuit intrinsically has a limit in tracking large data rate variations. The PLL-based CDR circuit utilizes a ring Voltage Controlled Oscillator (VCO), which is not suitable for super-high data rate (e.g., higher than 25 Gbps) application, because a jitter as a large portion of a Unit Interval (UI) present in the CDR circuit adversely impacts Bit Error Rate (BER). For example, the CDR may fail to lock to data when a real data rate differs beyond a certain limit (e.g. >5000 ppm) from the expected data rate, and produce incorrect (late/early) detection of clock edge versus data edge. In addition, a chip area required for the CDR circuit and skew variations among multiple phases in the CDR circuit are important factors.